RM // VLSI
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VLSI Design & Verification Engineer

Hi, I'm Rahul Macha

I verify complex silicon.

Dedicated to designing synthesizable RTL design blocks and building robust, coverage-driven UVM verification environments. Specializing in SystemVerilog, formal SVA assertions, and Linux-based EDA toolchains.

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Verified Toolchain & Environments

SystemVerilog UVM 1.2 QuestaSim Synopsys Verdi Xilinx Vivado Linux CLI
Rahul Macha
PROFILE & ARCHITECTURAL FOUNDATION

About Me & Silicon Methodology

Bridging synthesizable RTL design implementation with mathematically rigorous, coverage-driven verification.

Architecting Bug-Free Silicon

I specialize in identifying corner-case RTL design bugs before silicon tapeout through coverage-driven Universal Verification Methodology (UVM) and SystemVerilog Assertions (SVA).

Currently serving as a Student Trainee in VLSI Digital Engineering at VLSI FIRST (Hyderabad). Graduate in Electronics and Communication Engineering from BIHER.

98.4%+ Coverage Goal
7+ FIFO Testcases
ℹ
Interactive Architecture: Click any block in the schematic to inspect its active responsibility.
Layered UVM Verification & DUT Architecture SYNTHESIZABLE DUT
UVM VERIFICATION ENVIRONMENT (tb_env) Sequencer seq_item queue UVM Driver TLM -> Pin Level UVM Monitor Passive Observer Scoreboard Golden Reference Match / Mismatch Functional Coverage & SVA Checker covergroup cg_fifo • assert property(no_overflow) Virtual Interface (vif) RTL DESIGN (DUT) Verilog / Synthesizable Synchronous FIFO Core APB Slave Interface Control FSM / Regs
Scoreboard & Golden Reference Model: Compares DUT outputs against a golden software predictor, verifying data ordering, packet integrity, and latency.
INDUSTRY APPRENTICESHIP

Professional Journey

Apprenticeship · Present

Trainee · VLSI FIRST

Student Trainee | VLSI Digital Engineering

Feb 2026 – Present • 9 mos
Hyderabad, Telangana, India · On-site
RTL Design & Verification

Developing and simulating digital logic blocks (ALU, FIFO, UART) using Verilog and SystemVerilog.

Design Flow

Hands-on execution across the ASIC/FPGA design flow, from RTL coding and functional simulation to logic synthesis.

Tools & Debugging

Proficient in using industry-standard EDA tools like QuestaSim for design implementation and waveform analysis.

CORE COMPETENCIES & TOOLCHAIN

Skills & Technical Domains

Core Hardware
Digital Design VLSI CMOS Digital Electronics FSM Architecture Timing Closure
HDLs & Verification
SystemVerilog UVM 1.2 Verilog SVA Assertions Functional Coverage OOP Testbenches
EDA Tools & Debug
Siemens QuestaSim Synopsys Verdi ModelSim Xilinx Vivado Synopsys VCS Waveform Debug
Protocols & OS
AMBA APB AXI4-Lite AHB-Lite Linux (CLI) Python Shell Scripting
PROTOCOL SPECIFICATIONS

Protocol Verification Matrix

AMBA APB 3/4

Peripheral Bus
Concurrent SVA Check Active Assertion
LIVE DIGITAL TIMING GENERATOR

Interactive Synchronous Waveform Viewer

CYCLE: #4 • Time: 40.0ns
FULL: 0 EMPTY: 0 OCCUPANCY: 3/8
clk
wr_en
rd_en
HARDWARE VERIFICATION

Featured Verification Projects

COMMUNICATION CHANNEL ACTIVE

Get In Touch

Looking for a dedicated VLSI Verification Engineer for your ASIC, FPGA, or IP core teams? Send a message directly.

Direct Email
rahulmachaw80@gmail.com
Current Status
Available for immediate call & interviews

Hyderabad, India • Open to on-site & hybrid relocation

Professional Handles: